 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Preliminary RF2162 3V 900MHZ LINEAR AMPLIFIER 2 Typical Applications * 3V CDMA/AMPS Cellular Handsets * 3V JCDMA/TACS Cellular Handsets * 3V TDMA/AMPS Cellular Handsets * Spread-Spectrum Systems * CDPD Portable Data Cards * Portable Battery-Powered Equipment 2 POWER AMPLIFIERS Product Description 3.75 2 0.45 0.28 0.75 0.50 0.80 TYP 1 1 The RF2162 is a high-power, high-efficiency linear amplifier IC targeting 3V handheld systems. The device is manufactured on an advanced Gallium Arsenide Heterojunction Bipolar Transistor (HBT) process, and has been designed for use as the final RF amplifier in dual-mode 3V CDMA/AMPS hand-held digital cellular equipment, spread-spectrum systems, and other applications in the 800MHz to 960MHz band. The RF2162 has an analog bias control voltage to maximize efficiency. The device is self-contained with 50 input and the output can be easily matched to obtain optimum power, efficiency, and linearity characteristics. The device is packaged in a compact 4mmx4mm, 16-pin, leadless chip carrier. 3.75 + 1.60 4.00 12 1.50 SQ INDEX AREA 3 3.20 4.00 1.00 0.90 0.75 0.65 NOTES: 1 Shaded Pin is Lead 1. 2 Dimension applies to plated terminal and is measured between 0.10 mm and 0.25 mm from terminal tip. 0.05 0.00 Dimensions in mm. The terminal #1 identifier and terminal numbering convention 3 shall conform to JESD 95-1 SPP-012. Details of terminal #1 identifier are optional, but must be located within the zone indicated. The identifier may be either a mold or marked feature. 4 5 Pins 1 and 9 are fused. Package Warpage: 0.05 max. Optimum Technology Matching(R) Applied Si BJT Si Bi-CMOS u Package Style: LCC, 16-Pin, 4x4 GaAs HBT SiGe HBT VCC BIAS GaAs MESFET Si CMOS Features * Single 3V Supply * 29dBm Linear Output Power * 29dB Linear Gain * 35% Linear Efficiency * On-board Power Down Mode * 800MHz to 960MHz Operation VCC1 VCC1 GND 1 GND GND RFIN 2 3 4 5 VREG1 16 15 14 13 12 11 10 RF OUT RF OUT RF OUT 6 VMODE 7 VREG2 8 BIAS GND 9 GND 2F0 Ordering Information RF2162 RF2162 PCBA 3V 900MHz Linear Amplifier Fully Assembled Evaluation Board Functional Block Diagram RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com Rev A17 011011 2-205 RF2162 Absolute Maximum Ratings Parameter Supply Voltage (RF off) Supply Voltage (POUT 31dBm) Mode Voltage (VMODE) Preliminary Rating +8.0 +4.5 +3.0 Unit VDC VDC VDC VDC dBm C C Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). 2 POWER AMPLIFIERS Control Voltage (VPD) Input RF Power Operating Case Temperature Storage Temperature Moisture Sensitivity +3.0 +12 -30 to +110 -30 to +150 Modified JEDEC Level 2 Parameter Overall Usable Frequency Range Typical Frequency Range Linear Gain Second Harmonic (including second harmonic trap) Max CW Output Power Total Efficiency (AMPS mode) Maximum Linear Output Power (CDMA Modulation) Total Linear Efficiency Adjacent Channel Power Rejection Noise Power Maximum Linear Output Power (CDMA Modulation) Total Efficiency (AMPS mode) Max CW Output Power Total Linear Efficiency Adjacent Channel Power Rejection Input VSWR Output Load VSWR Specification Min. Typ. Max. 800 28 824-849 29 -30 31.5 50 29 30 35 -46 -58 -90 29 50 30.5 36 -46 -58 <2:1 960 31 Unit Condition T=25C, VCC =3.4V, Freq=824MHz to 849MHz unless otherwise specified MHz MHz dB dBc dBm % dBm % dBc dBc dBm dBm % dBm % dBc dBc -44 -56 -89 ACPR @ 885kHz ACPR @1980kHz VCC =3.4V; BW =30kHz; RX Band NF measure from TX center band to RX center band. VCC =3.0V 30 30 31 -44 -56 10:1 ACPR @ 885kHz ACPR @ 1980kHz No damage. TDMA Linear Output Power Linear ACP Linear ALT CP Efficiency 30 -29 -49 46 3.4 135 10 dBm -28 -48 30kHZ offset 60kHZ offset O/P=30dBm V mA mA ns A V V V 45 3.0 Power Supply Power Supply Voltage Idle Current VREG Current Turn On/Off time Total Current (Power down) VREG "Low" Voltage VREG "High" Voltage VMODE Bias Control Voltage Range 4.5 200 15 <100 10 0.2 2.9 VMODE =0V to 0.5V Total pins 6 and 7, VREG =2.8V VPD =Low 2.7 0 2.8 0 to 2.5 2-206 Rev A17 011011 Preliminary Pin 1 2 3 4 Function GND GND1 GND1 RF IN Description Ground connection. Connect to package base ground. This ground should be isolated from the backside ground contact on top metal layer. Ground for stage 1. Keep traces physically short and connect immediately to ground plane for best performance. This ground should be isolated from the backside ground contact on top metal layer. Same as Pin 2. RF input. An external DC blocking capacitor is required if this port is connected to a DC path to ground or a DC voltage. RF2162 Interface Schematic VCC1 2 POWER AMPLIFIERS RF IN From Bias Stages GND1 5 VREG1 6 7 VMODE VREG2 8 9 10 GND GND RF OUT Enable voltage for first stage. When this pin is "low", all circuits are shut off. When this pin is 2.8V, all circuits are operating normally. VREG requires a regulated 2.8V for the amplifier to operate properly over all specified temperature and voltage ranges. A dropping resistor from a higher regulated voltage may be used to provide the required 2.8V. A 100pF high frequency bypass capacitor is recommended. This is an analog bias current control pin. The range is 0V for minimum bias to 3.0 for maximum bias. Enable voltage for second or output stage. When this pin is "low", all circuits are shut off. When this pin is 2.8V, all circuits are operating normally. VREG requires a regulated 2.8V for the amplifier to operate properly over all specified temperature and voltage ranges. A dropping resistor from a higher regulated voltage may be used to provide the required 2.8V. A 100pF high frequency bypass capacitor is recommended. Bias circuitry ground. See application schematic. Ground connection. Connect to package base ground. This ground should be isolated from the backside ground contact on top metal layer. RF output and power supply for the output stage. The bias for the output stage is provided through this pin and pin 13. An external matching network is required to provide the optimum load impedance; see the application schematics for details. Same as pin 10. Same as pin 10. Harmonic trap. This pin connects to the RF output but is used for providing a low impedance to the second harmonic of the operating frequency. An inductor or transmission line resonating with an on chip capacitor at 2fo is required at this pin. Power supply for bias circuitry. A 100pF high frequency bypass capacitor is recommended. Interstage tuning and bias supply for first stage. Interstage tuning and bias supply for first stage. Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias. The pad should have a short thermal path to the ground plane. See pin 10. RF OUT From Bias Stages 11 12 13 RF OUT RF OUT 2FO 14 15 16 Pkg Base VCC BIAS VCC1 VCC1 GND Rev A17 011011 2-207 RF2162 Application Schematic - US CDMA VCC 100 pF 10 nF Preliminary Bypassing for VCC 2 POWER AMPLIFIERS Interstage tuning for centering frequency response 100 pF 2nd Harmonic Trap TL3 1.8 nH 1 nH 100 pF TL4 14 13 12 11 10 TL1 TL2 9.1 pF** 100 pF RF OUT 5.1 pF** Matching network for optimum load impedance 1 100 pF To Vary Gain 16 15 27 nH* 1 pF 2 3 4 100 pF RF IN 15 nH Matching network for optimum input return loss 330 5 0 100 pF 6 7 8 9 10 nH Bias Return 0 100 pF Bypassing for VREG1 and V REG2 VREG 1 k VMODE * High Q inductor (i.e., Coilcraft 0805HQ-series). **High Q capacitors (i.e., Johanson C-series). 2-208 Rev A17 011011 Preliminary Application Schematic - US TDMA P1-1 10 nF C30 Interstage tuning for centering frequency response RF2162 100 pF Bypassing for VCC 2nd Harmonic Trap 2 POWER AMPLIFIERS TL3 100 pF RF OUT TL5 1.5 nH 3.6 pF 100 pF TL7 14 13 12 11 10 TL1 TL2 12 pF** 1.5 nH 1 100 pF 2 3 4 100 pF 15 nH Matching network for optimum input return loss 16 15 16 nH* 1 pF To Vary Gain 820 RF IN 4.7 pF** 5 0 100 pF 6 7 8 9 27 nH Bias Return Matching network for optimum load impedance 100 pF Bypassing for VREG1 and VREG2 VREG * L1 is a High Q inductor (i.e.,Coilcraft 0805HQ-series). **C1 and C14 are High Q capacitors (i.e., Johanson C-series). 1 k VMODE Rev A17 011011 2-209 RF2162 (Download Bill of Materials from www.rfmd.com.) P1-1 C2 4.7 uF Preliminary Evaluation Board Schematic - US CDMA 2 POWER AMPLIFIERS P1-1 P1 1 2 VCC GND C25 4.7 F C30 C6 100 pF TL4 C28 10 nF C4 100 pF P2 P2-1 P2-2 1 2 VREG VMODE L3 1.8 nH TL3 1 C18 100 pF 2 3 4 L2 15 nH C27 100 pF C10 4.7 F 5 R3 0 R4 0 C13 100 pF 6 7 8 16 15 14 13 12 11 10 9 L4 18 nH L5 1 nH TL5 C17 1 pF C3 100 pF L1* TL1 TL2 C1** J1 RF IN C5 100 pF R2 J4 RF OUT C14** 2162400B P2-1 R1 1 k P2-2 * L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series). **C1 and C14 are High Q capacitors (i.e., Johanson C-series). Board CDMA (US) Transmission Line Length CDMA (US) R2 () 330 C30 (pF) 100 C1 (pF) 9.1 L1 (nH) 27 C14 (pF) 5.1 TL1 175 mils TL2 165 mils TL3 L=15 mils W=16 mils TL4 L=40-45 mils from L3 W=16 mils TL5 L=15-20 mils W=14 mils 2-210 Rev A17 011011 Preliminary Evaluation Board Schematic - US TDMA P1-1 C2 4.7 uF P1-1 C28 10 nF C6 100 pF C55 3.6 pF C4 100 pF RF2162 P1 1 2 P2 P2-1 P2-2 1 2 VREG VMODE VCC GND C25 1 F C30 TL5 2 POWER AMPLIFIERS Er = 4.7 H = 14 mils t = 1 mil 1 C18 100 pF 2 3 4 L2 15 nH C27 100 pF R3 0 5 6 L3 1.5 nH TL4 16 15 TL6 14 13 12 11 10 7 R1 1 k 8 C13 100 pF R4 0 9 TL7 C17 1 pF L10 1.5 nH C3 100 pF L1* TL1 TL2 C1** TL3 J1 RF IN C5 100 pF R2 J4 RF OUT C14** L4 27 nH 2162401B P2-2 P2-1 * L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series). **C1 and C14 are High Q capacitors (i.e., Johanson C-series). Board TDMA (US) Transmission Line Length TDMA (US) R2 () 820 C30 (pF) 56 C1 (pF) 12 L1 (nH) 16 C14 (pF) 5.6 TL1 90 mils TL2 82 mils TL3 135 mils TL4 L=12 mils W=16 mils TL5 L=49 mils W=16 mils TL6 L=12 mils TL7 L=12 mils W=14 mils Rev A17 011011 2-211 RF2162 Evaluation Board Layout - CDMA Board Size 2.0" x 2.0" Board Thickness 0.031", Board Material FR-4 Preliminary 2 POWER AMPLIFIERS 2-212 Rev A17 011011 Preliminary Evaluation Board Layout - TDMA RF2162 2 POWER AMPLIFIERS Rev A17 011011 2-213 RF2162 Preliminary 2 POWER AMPLIFIERS 2-214 Rev A17 011011 |
Price & Availability of RF2162PCBA
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |